555 Timer IC

555 TIMER IC

 

555 IC is that the famous clock IC wired within the Astable mode. Resistors R1, VR2 and capacitor C1 approach because the planning parts and therefore the yield beats are accessible from the yield pin 3. These heartbeats are given to the data pin 14 of the counter IC 74154N. Out of the ten yields of IC 74154N, eight yields are utilized to drive the LEDs. The ninth yield pin 9 is related to the reset pin 15 to prevent the checking. that the cycle rehashes. With the estimation of C1, each LED stays on for 1second. At the purpose when one LED kills, the second on activates. This cycle continues giving the light source appearance. Resistor R3 keeps the data pin 14 of IC2 low after each pulse.VR1 changes the speed of LED pursuing.

 

 

 

Pin Configuration of the 555 Timer

 

Pin 1 (Ground): Associates with the 0v power flexibly.

 

Pin 2 (Trigger): Identifies 1/3 of VCC to create yield HIGH. Pin 2 has command over pin 6. within the event that pin 2 is LOW, and pin 6 LOW, yield proceeds to stay HIGH. On the off chance that pin 6 HIGH, and pin 2 goes LOW, yield goes LOW while pin 2 LOW. This pin features a high impedance (about 10M) and can trigger with about 1uA.

 

Pin 3 (Output): (Pins 3 and seven are "in stage.") Goes HIGH (about 2v not exactly VCC) and LOW (about 0.5v under 0v) and can convey up to 200mA.

 

Pin 4 (Reset): Inside associated HIGH by means of 100k. Must be taken beneath 0.8v to reset the chip.When the negative heartbeat is applied to the current pin to cripple or reset, a bogus activating is disregarded by associating with VCC.

 

Pin 5 (Control): A voltage applied to the present pin will change the design of the RC network.The control voltage pin accustomed control the beat yield waveform and levels of edge and trigger. At the purpose when an outer voltage is applied to the present pin, at that time the yield waveform are tweaked

 

Pin 6 (Threshold): Recognizes 2/3 of VCC to form yield LOW just if pin 2 is HIGH. This pin has an exceptionally high impedance (about 10M) and can trigger with about 0.2uA.

 

Pin 7 (Discharge): Goes LOW when pin 6 identifies 2/3 VCC yet pin 2 must be HIGH. On the off chance that pin 2 is HIGH, pin 6 are often HIGH or LOW and pin 7 stays LOW. Goes OPEN (HIGH) and remains HIGH when pin 2 distinguishes 1/3 VCC (even as a coffee heartbeat) when pin 6 is LOW. (Pins 7 and three are "in stage.") Pin 7 is such as stick 3 however pin 7 doesn't go high - it goes OPEN. Be that because it may, it goes LOW and can sink about 200mA.

 

Pin 8 (Supply): Interfaces with the positive force gracefully (Vs). this may be any voltage somewhere within the range of 4.5V and 15V DC, yet is sometimes 5V DC when working with advanced ICs.

 

 

IC 555 clock : Astable Mode

 

Notice: ▪ 2 resistors ▪ 1 capacitor ▪ OUTPUT is square wave beat

 

Astable method of 555 clock IC is additionally called Free running or self-activating mode. Dissimilar to Monostable Multivibrator mode it doesn't have any steady state, it's two semi stable state (HIGH and LOW). No outer activating is required in Astable mode, it consequently trade its two states on a selected stretch, thus creates an oblong waveform. this point length of HIGH and LOW yield has been controlled by the outer resistors (R1 and R2) and a capacitor(C1). Astable mode functions as an oscillator circuit, during which yield sway at a selected recurrence and produce beats in rectangular wave form.Using 555 clock IC, we are able to create time span of HIGH and LOW yield, from small scale seconds to hours, that's the explanation 555 is mainstream

 

Activity of Astable Multivibrator method of 555 clock IC:

 

When initially force is turned ON, Trigger Pin voltage is underneath 1/3 Vcc, that produces the lower comparator yield HIGH and SETS the flip failure and yield of the 555 chip is HIGH.

 

This makes the transistor Q1 OFF//, in light of the actual fact that Qbar, Q'=0 is legitimately applied to base of transistor.//As the transistor is OFF, capacitor C1 begins charging and when it gets charged to a voltage above than 1/3 Vcc, at that time Lower comparator yield seems to be LOW (Upper comparator is additionally at LOW) and Flip failure yield continues as before as past (555 yield stays HIGH).

 

Presently when capacitor charging gets to voltage above than 2/3Vcc, at that time the voltage of non-upsetting end (Threshold PIN 6) gets more than the rearranging end of the comparator. This makes Upper comparator yield HIGH and RESETs the Flip lemon, yield of 555 chip seems to be LOW.

 

When the yield of 555 get LOW methods Q'=1, at that time transistor Q1 becomes ON and short the capacitor C1 to the bottom. therefore the capacitor C1 begins releasing to the bottom through the Discharge PIN 7 and resistor R2.

 

As capacitor voltage get down beneath the 2/3 Vcc, upper comparator yield seems to be LOW, presently SR Flip failure stays within the past state as both the comparators are LOW.

 

While releasing, when capacitor voltage gets down underneath 1/3 Vcc, this makes the Lower comparator yield HIGH (upper comparator stay LOW) and Sets the flip lemon again and 555 yield seems to be HIGH.

 

Transistor Q1 gets OFF and again capacitor C1 begins charging

 

 

Why stable or what's steady mode?

This charging and releasing of capacitor proceeds and an oblong swaying yield wave for is made. While capacitor is getting charge the yield of 555 is HIGH, and keeping in mind that capacitor is getting release yield are going to be LOW. So this can be called Astable mode since none of the state is steady and 555 consequently trade its state from HIGH to LOW and LOW to HIGH, so it's called Free running Multivibrator.

 

Time High (Seconds) T1 = 0.693 * (R1+R2) * C1

 

Time Low (Seconds) T2 = 0.693 * R2 * C1

 

Timeframe T = Time High + Time Low = 0.693 * (R1+2*R2) * C1

 

Freqeuncy f = 1/Time Period = 1/0.693 * (R1+2*R2) * C1 = 1.44/(R1+2*R2) * C1

 

Obligation Cycle: Duty cycle is that the proportion of your time that the yield is HIGH to absolutely the time.

 

Obligation cycle %: (Time HIGH/Total time) * 100 = (T1/T) * 100 = (R1+R2)/(R1+2*R2) *100

 

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Monostable multivibrator (MMV) method of 555 clock IC is likewise called Single shot mode. because the name demonstrates, only one state is steady and therefore the other one is termed flimsy state. 555 clock IC stays in Stable state until the surface activating is applied. an out of doors activating is required for change from Stable to unsteady state. 555 IC consequently switches back to stable state after it slow, this time, that the 555 remains in semi stable state, is dictated when steady of RC organize within the circuit. This outside activating is given by associating the Trigger PIN 2 to the bottom utilizing a push.

 

 

What is J-K Flip-flop?

The JK flip lemon is basically a gated SR flip-flop with the expansion of a clock input hardware that forestalls the unlawful or invalid yield condition that may happen when the 2 sources of information S and R are appreciate rationale level "1"

 

What is the employment of JK flip lemon?

JK Flip Flop may be a general flip-flop that creates the circuit switch between two states and is broadly utilized in move registers, counters, PWM and PC applications

 

What is a counter?

Counter may be a consecutive circuit. A computerized circuit which is used for an including beats is thought counter

Sorts of Electronic Counters

 

Simultaneous counter.

Nonconcurrent Counter or Ripple Counter.

Up/Down Counter.

Decade Counter.

Ring counter.

Fell counter.

Johnson counter.

Modulus counter.

 

All ensuing flip-flops are timed by the yield of the previous flip-flop. Offbeat counters are additionally called swell counters seeable of the style during which the clock beat swells it route through the flip-flops.